# params

name: base_mac
tlv_name: nv_base_mac_guid
offset: 0x0.24
size: 0x8.0
type: BYTES
description:
The base MAC address of the device. The MAC addresses for \;the PCI physical functions of all the network ports are derived \;from the base MAC.\;Offset 00h, bits 15..0 hold bits 47..32 of the MAC address.\;Offset 04h, bits 31..0 hold bits 31..0 of the MAC address.


name: base_guid
tlv_name: nv_base_mac_guid
offset: 0x8.24
size: 0x8.0
type: BYTES
description:
The base InfiniBand GUID. The InfiniBand addresses for the \;PCI physical functions of all the network ports are derived \;from the base GUID.


name: min_allowed_fw_version
tlv_name: nv_forbidden_versions
offset: 0x8.0
size: 0x4.0
type: BINARY
description:
The minimal (earliest) firmware version priori to which \;the device must refuse update.\;Bits 31..24 - Major version\;bits 23..16: Minor version\;Bits 15..0 - Sub-minor version


name: forbidden_fw_version
tlv_name: nv_forbidden_versions
offset: 0x10.0
size: 0x80.0
type: BINARY
description:
A list of FW versions to which the device must refuse \;update. The FW version format is identical to the one \;shown in min_allowed_fw_version description.\;The list has up to 32 entries and is terminated by an \;entry set to 0x0.


name: log_memic_bar_size
tlv_name: nv_memic_conf
offset: 0x0.0
size: 0x0.8
type: UNSIGNED
mlxconfig_name: MEMIC_BAR_SIZE
dependency: $nv_memic_cap.max_memic_size_limit!=0
max_val: $nv_memic_cap.max_log_memic_bar_size
description:
The amount of BAR size assigned for MEMIC. The size in bytes \;is memic_size_limit*2^log_memic_bar_size.


name: memic_size_limit
tlv_name: nv_memic_conf
offset: 0x0.8
size: 0x0.4
type: ENUM
textual_values: DISABLED=0x0,_256KB=0x1,_512KB=0x2,_1024KB=0x3
mlxconfig_name: MEMIC_SIZE_LIMIT
dependency: $nv_memic_cap.max_memic_size_limit!=0
max_val: $nv_memic_cap.max_memic_size_limit
description:
The maximum amount of internal device memory that can be \;consumed by the MEMIC application.\;0x0: DISABLED\;0x1: _256KB\;0x2: _512KB\;0x3: _1024KB


name: max_memic_size_limit
tlv_name: nv_memic_cap
offset: 0x0.8
size: 0x0.4
type: ENUM
textual_values: DISABLED=0x0,_256KB=0x1,_512KB=0x2,_1024KB=0x3
description:
The maximum value allowed for memic_size_limit.\;0x0: DISABLED\;0x1: _256KB\;0x2: _512KB\;0x3: _1024KB


name: log_num_descriptor
tlv_name: nv_host_chaining_conf
offset: 0x4.24
size: 0x8.0
type: UNSIGNED
mlxconfig_name: HOST_CHAINING_DESCRIPTORS
description:
Log(base 2) of the number of packets descriptors that should be \;allocated by the host for host chaining for a given IEEE802.1p \;priority i.\;0 means that no descriptors are allocated for this priority and traf\;fic with this priority will be dropped.


name: log_data_size
tlv_name: nv_host_chaining_conf
offset: 0xC.24
size: 0x8.0
type: UNSIGNED
mlxconfig_name: HOST_CHAINING_TOTAL_BUFFER_SIZE
description:
Log(base 2) of the buffer size (in bytes) allocated for host chain\;ing for a given IEEE802.1p priority i.\;0 means no buffer for this priority and traffic with this priority \;will be dropped.


name: cache_disable_supported
tlv_name: nv_host_chaining_cap
offset: 0x0.30
size: 0x0.1
type: BOOL
description:
When TRUE, caching of host chaining data can be disabled by \;cache_disable in NV_HOST_CHAINING_CONF.


name: log_max_total_data_size
tlv_name: nv_host_chaining_cap
offset: 0x4.16
size: 0x0.8
type: UNSIGNED
description:
Log(base 2) of the maximal total data buffer size allocated for \;host chaining (sum of all priorities)


name: log_max_total_num_descriptors
tlv_name: nv_host_chaining_cap
offset: 0x4.24
size: 0x0.8
type: UNSIGNED
description:
Log2 of the maximal total number of packet descriptors allocated \;for host chaining (sum of all priorities).


name: internal_cpu_model
tlv_name: nv_internal_cpu_conf
offset: 0x0.0
size: 0x0.4
type: ENUM
textual_values: SEPERATED_HOST=0x0,EMBEDDED_CPU=0x1
mlxconfig_name: INTERNAL_CPU_MODEL
dependency: ignore_dependency
description:
Select the model for the Internal CPU\;0x0: SEPERATED_HOST - Supported only when NV_INTER\;NAL_CPU_CAP.separate_host_model_supported==1.\;0x1: EMBEDDED_CPU - Supported only when NV_INTER\;NAL_CPU_CAP.embedded_cpu_model_supported==1.\;other values are reserved\;This NVCONFIG parameter can only be configured from the \;embedded CPU.


name: flex_parser_profile_enable
tlv_name: nv_flex_parser_conf
offset: 0x0.0
size: 0x0.8
type: UNSIGNED
mlxconfig_name: FLEX_PARSER_PROFILE_ENABLE
description:
Indicates which flex parser profile to enable. Each profile sup\;ports a set of protocols. The support indication and the set of pro\;tocols supported by profile 'x' reported in \;NC_FLEX_PARSER_CAP.flex_parser_profile_x_supported.

dependency:
($nv_flex_parser_cap.flex_parser_profile_0_supported==1)||($nv_flex_parser_cap.flex_parser_profile_1_supported==1)||($nv_flex_parser_cap.flex_parser_profile_2_supported==1)||($nv_flex_parser_cap.flex_parser_profile_3_supported==1)||($nv_flex_parser_cap.flex_parser_profile_4_supported==1)||($nv_flex_parser_cap.flex_parser_profile_5_supported==1)||($nv_flex_parser_cap.flex_parser_profile_6_supported==1)

rule:
($flex_parser_profile_enable==0 && $nv_flex_parser_cap.flex_parser_profile_0_supported==1) || ($flex_parser_profile_enable==1 && $nv_flex_parser_cap.flex_parser_profile_1_supported==1) || ($flex_parser_profile_enable==2 && $nv_flex_parser_cap.flex_parser_profile_2_supported==1) || ($flex_parser_profile_enable==3 && $nv_flex_parser_cap.flex_parser_profile_3_supported==1) || ($flex_parser_profile_enable==4 && $nv_flex_parser_cap.flex_parser_profile_4_supported==1) || ($flex_parser_profile_enable==5 && $nv_flex_parser_cap.flex_parser_profile_5_supported==1)|| ($flex_parser_profile_enable==6 && $nv_flex_parser_cap.flex_parser_profile_6_supported==1)


name: prog_parse_graph
tlv_name: nv_flex_parser_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: PROG_PARSE_GRAPH
dependency: ($nv_flex_parser_cap.prog_parse_graph_supported==1)
description:
When TRUE, the device parse graph may be dynamically config\;ured. The amount of programmable resources is reduced accord\;ing to the amount of protocols already supported by \;FLEX_PARSER_PROFILE_ENABLE.


name: flex_ipv4_over_vxlan_port
tlv_name: nv_flex_parser_conf
offset: 0x8.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: FLEX_IPV4_OVER_VXLAN_PORT
dependency: ignore_dependency
description:
The UDP port for incoming IPoVxLAN traffic (non-standard).\;When set, also affects flex_vxlan_gpe_supported when enabled \;on same profile.\;


name: prog_parse_graph_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.0
size: 0x0.1
type: BOOL
description:
When TRUE, indicated dynamic programming of the device \;parse graph may be enabled using PROG_ PARSE_GRAPH.


name: flex_parser_profile_6_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.25
size: 0x0.1
type: BOOL
description:
When TRUE, profile 6 is supported and can be enabled by NV_\;FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;flex_vxlan_pad_supported (VXLAN header is padded with addi\;tional DWs according to the 8 bit next to the VNI)\;flex_icmp_supported\;flex_icmpv6_supported


name: flex_parser_profile_5_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.26
size: 0x0.1
type: BOOL
description:
When TRUE, profile 5 is supported and can be enabled by NV_\;FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;IPoIB_UD_QP


name: flex_parser_profile_4_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.27
size: 0x0.1
type: BOOL
description:
When TRUE, profile 4 is supported and can be enabled by NV_\;FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows no additional protocols, keeping all \;programmable parsing resources free


name: flex_parser_profile_3_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.28
size: 0x0.1
type: BOOL
description:
If set, indicates profile 3 is supported and can be enabled by \;NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;GTP-U


name: flex_parser_profile_2_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.29
size: 0x0.1
type: BOOL
description:
If set, indicates profile 2 is supported and can be enabled by \;NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;flex_vxlan_gpe_supported\;flex_ipv4_over_vxlan_supported\;flex_icmp_supported\;flex_icmpv6_supported


name: flex_parser_profile_1_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.30
size: 0x0.1
type: BOOL
description:
If set, indicates profile 1 is supported and can be enabled by \;NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;\;flex_geneve_supported\;flex_ctrl_word_over_mpls_over_gre_supported\;flex_ctrl_word_over_mpls_over_udp_supported\;flex_geneve_tlv_option_0_supported


name: flex_parser_profile_0_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
If set, indicates profile 0 is supported and can be enabled by \;NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;\;flex_geneve_supported\;flex_ipv4_over_vxlan_supported\;flex_ipv4_over_ip_supported\;flex_ipv6_over_ip_supported\;flex_vxlan_gpe_supported\;flex_geneve_tlv_option_0_supported


name: log_hpin_num_descriptor
tlv_name: nv_internal_hairpin_conf
offset: 0x0.24
size: 0x8.0
type: UNSIGNED
mlxconfig_name: ESWITCH_HAIRPIN_DESCRIPTORS
description:
Log(base 2) of the number of packets descriptors allocated inter\;nally for hairpin for a given IEEE802.1p priority i.\;0 means that no descriptors are allocated for this priority and traf\;fic with this priority will be dropped.


name: log_hpin_data_size
tlv_name: nv_internal_hairpin_conf
offset: 0x8.24
size: 0x8.0
type: UNSIGNED
mlxconfig_name: ESWITCH_HAIRPIN_TOT_BUFFER_SIZE
description:
Log(base 2) of the buffer size (in bytes) allocated internally for \;hairpin for a given IEEE802.1p priority i.\;0 means no buffer for this priority and traffic with this priority \;will be dropped.


name: log_max_hpin_num_descriptor_per_prio
tlv_name: nv_internal_hairpin_cap
offset: 0x0.8
size: 0x0.8
type: UNSIGNED
description:
Log(base 2) of the maximal number of packet descriptors allo\;cated for eswitch hairpin per priority


name: log_max_hpin_total_data_size
tlv_name: nv_internal_hairpin_cap
offset: 0x0.16
size: 0x0.8
type: UNSIGNED
description:
Log(base 2) of the maximal total data buffer size allocated for \;eswitch hairpin (sum of all priorities)


name: log_max_hpin_total_num_descriptors
tlv_name: nv_internal_hairpin_cap
offset: 0x0.24
size: 0x0.8
type: UNSIGNED
description:
Log2 of the maximal total number of packet descriptors allocated \;for eswitch hairpin (sum of all priorities).


name: non_prefetchable_pf_bar
tlv_name: nv_global_pci_conf
offset: 0x0.17
size: 0x0.1
type: BOOL
mlxconfig_name: NON_PREFETCHABLE_PF_BAR
dependency: $nv_global_pci_cap.non_prefetchable_pf_bar_supported==1
valid_bit: non_prefetchable_pf_bar_valid
description:
When set, the PF BAR prefetchable bit is cleared.\;Note: PCI switches and operation systems have dedicated quotas \;for non-prefetchable memory, hence, you may need to decrease \;log_pf_uar_bar_size to enable this feature.


name: per_pf_num_msix
tlv_name: nv_global_pci_conf
offset: 0x0.19
size: 0x0.1
type: BOOL
mlxconfig_name: PER_PF_NUM_MSIX
description:
When TRUE, the MSI-X configuration is defined by NUM_P\;F_MSIX for each PF individually. In case they are not defined for \;a PF, device defaults are used.\;When FALSE, the MSI-X configuration is defined by device \;defaults\;Valid only when NUM_PF_MSIX_VALID is set to FALSE.


name: per_pf_num_sf
tlv_name: nv_global_pci_conf
offset: 0x0.20
size: 0x0.1
type: BOOL
mlxconfig_name: PER_PF_NUM_SF
dependency: $nv_global_pci_cap.per_pf_num_sf_supported == 1
description:
When TRUE, the SFs configuration is defined by TOTAL_SF \;and SF_BAR_SIZE for each PF individually. In case they are not \;defined for a PF, device defaults are used. \;When FALSE, the SFs configuration is defined by device \;defaults.\;Valid only when PF_BAR2_ENABLE is set to FALSE.


name: vf_nodnic_enable
tlv_name: nv_global_pci_conf
offset: 0x0.22
size: 0x0.1
type: BOOL
mlxconfig_name: VF_NODNIC_ENABLE
dependency: $nv_global_pci_cap.vf_nodnic_supported == 1
description:
When set to TRUE, VF has VSC Gateway exposed through PCI, \;and may access the NODNIC initialization segment


name: non_prefetchable_pf_bar_valid
tlv_name: nv_global_pci_conf
offset: 0x0.23
size: 0x0.1
type: BOOL
description:
When set to TRUE, non_prefetchable_bar field and \;allow_large_non_prefetchable_pf_bar overrides the default \;value.


name: pf_bar_size_valid
tlv_name: nv_global_pci_conf
offset: 0x0.24
size: 0x0.1
type: BOOL
description:
When set, the pf_bar_size field is valid. \;When cleared, the device uses the "factory_settings" value.


name: vf_bar_size_valid
tlv_name: nv_global_pci_conf
offset: 0x0.25
size: 0x0.1
type: BOOL
description:
When set, the vf_bar_size field is valid. \;When cleared, the device uses the "factory_settings" value.


name: num_pf_msix_valid
tlv_name: nv_global_pci_conf
offset: 0x0.26
size: 0x0.1
type: BOOL
mlxconfig_name: NUM_PF_MSIX_VALID
description:
When set, the num_pf_msix field is valid. \;When cleared, the number of PF MSI-X is defined by PER_P\;F_NUM_MSIX


name: num_vf_msix_valid
tlv_name: nv_global_pci_conf
offset: 0x0.27
size: 0x0.1
type: BOOL
description:
When set, the num_vf_msix field is valid. \;When cleared, the device uses the "factory_settings" value.


name: full_vf_qos_valid
tlv_name: nv_global_pci_conf
offset: 0x0.30
size: 0x0.1
type: BOOL
description:
When set, the full_vf_qos field is valid. \;When cleared, the device uses the "factory_settings" value.


name: total_vfs
tlv_name: nv_global_pci_conf
offset: 0x4.0
size: 0x0.16
type: UNSIGNED
description: The total number of Virtual Functions (VFs) that can be sup\;ported, for each PF.
mlxconfig_name: NUM_OF_VFS
dependency: $nv_global_pci_cap.sriov_support==1
valid_bit: sriov_valid
max_val: $nv_global_pci_cap.max_vfs_per_pf_valid==1 ? $nv_global_pci_cap.max_vfs_per_pf : 0
temp_vars:
$_calculatedTotalBar=($fpp_en==1?(log2($nv_global_pci_cap.max_total_bar==0?1:(($nv_global_pci_cap.max_total_bar/$num_pfs - ($log_pf_uar_bar_size)^2) / $total_vfs))) : (log2($nv_global_pci_cap.max_total_bar==0?1:(($nv_global_pci_cap.max_total_bar - ($log_pf_uar_bar_size)^2) / $total_vfs))))

rule:
(($nv_global_pci_cap.max_total_msix_valid==0)||($nv_global_pci_cap.max_total_msix==0)||(($num_pfs * ($num_pf_msix + $total_vfs * $num_vf_msix))<=$nv_global_pci_cap.max_total_msix)) && (($nv_global_pci_cap.max_total_bar_valid==0)||($nv_global_pci_cap.max_total_bar==0)||($sriov_en==0)||($_calculatedTotalBar<=$nv_global_pci_cap.max_total_bar))


name: num_pfs
tlv_name: nv_global_pci_conf
offset: 0x4.16
size: 0x0.8
type: UNSIGNED
dependency: $nv_global_pci_cap.num_pfs_supported==1
valid_bit: num_pfs_valid
min_val: 1
max_val: $nv_global_pci_cap.max_num_pfs
description:
Total number of PCIe functions (PFs) exposed by the device. The \;number of PFs must be a multiple of the number of ports, \;num_port_cap. Value 0 is only supported when an Emulated PCI \;Switch is present.


name: partial_wr_cache_mode
tlv_name: nv_global_pci_conf
offset: 0x4.24
size: 0x0.3
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,DISABLED=0x1,FUNCTION_BASED=0x2,ADDRESS_BASED=0x3
mlxconfig_name: PARTIAL_WRITE_CACHE_MODE
description:
Specifies the mode of operation for PCI write cache, for partial \;cacheline writes:\;0x0: DEVICE_DEFAULT - device default configuration\;0x1: DISABLED\;0x2: FUNCTION_BASED\;0x3: ADDRESS_BASED\;other values are reserved

dependency:
($nv_global_pci_cap.partial_wr_cache_mode_function==1) || ($nv_global_pci_cap.partial_wr_cache_mode_address==1)

rule:
(($partial_wr_cache_mode==0) || ($partial_wr_cache_mode==1) || ($partial_wr_cache_mode==2 && $nv_global_pci_cap.partial_wr_cache_mode_function==1) || ($partial_wr_cache_mode==3 && $nv_global_pci_cap.partial_wr_cache_mode_address==1))


name: pf_bar2_en
tlv_name: nv_global_pci_conf
offset: 0x4.27
size: 0x0.1
type: BOOL
mlxconfig_name: PF_BAR2_ENABLE
dependency: $nv_global_pci_cap.pf_bar2_supported == 1
description:
When TRUE, BAR2 is exposed on all external host PFs (but not \;on the embedded ARM PFs/ECPFs). The BAR2 size is defined \;by the log_pf_bar2_size.\;When FALSE, the SFs and BAR2 configurations are defined by \;PER_PF_NUM_SF


name: hide_port2_pf
tlv_name: nv_global_pci_conf
offset: 0x4.28
size: 0x0.1
type: BOOL
mlxconfig_name: HIDE_PORT2_PF
dependency: $nv_global_pci_cap.hide_port2_pf_supported != 0
description:
When TRUE, the device will not advertise the PFs associated \;with port 2, except for the Embedded CPU (ECPF) if exists. This \;configuration is available only when NV_PCI_\;CONF.ADVANCED_PCI_SETTINGS is TRUE.


name: fpp_en
tlv_name: nv_global_pci_conf
offset: 0x4.29
size: 0x0.1
type: BOOL
mlxconfig_name: FPP_EN
dependency: $nv_global_pci_cap.fpp_support==1
valid_bit: fpp_valid
description:
When this bit is cleared, the device exposes a single PCI function \;for both ports. When set, the device exposes one or more PCI \;functions for each port (this is the only mode supported by Con\;nectX-4 devices).


name: log_pf_uar_bar_size
tlv_name: nv_global_pci_conf
offset: 0x8.0
size: 0x0.6
type: UNSIGNED
description: Log 2 of the size of a PF"s UAR BAR in MBs.
mlxconfig_name: PF_LOG_BAR_SIZE
dependency: $nv_global_pci_cap.pf_bar_size_supported==1
valid_bit: pf_bar_size_valid
max_val: $nv_global_pci_cap.max_log_pf_uar_bar_size
temp_vars:
$_calculatedTotalBar=($fpp_en==1?(log2($nv_global_pci_cap.max_total_bar==0?1:(($nv_global_pci_cap.max_total_bar/$num_pfs - ($log_pf_uar_bar_size)^2) / $total_vfs))) : (log2($nv_global_pci_cap.max_total_bar==0?1:(($nv_global_pci_cap.max_total_bar - ($log_pf_uar_bar_size)^2) / $total_vfs))))

rule:
($nv_global_pci_cap.max_total_bar_valid==0)||($nv_global_pci_cap.max_total_bar==0)||($sriov_en==0)||($_calculatedTotalBar<=$nv_global_pci_cap.max_total_bar)


name: num_pf_msix
tlv_name: nv_global_pci_conf
offset: 0x8.12
size: 0x0.10
type: UNSIGNED
description: Number of MSI-X vectors and EQs per PF.
mlxconfig_name: NUM_PF_MSIX
dependency: $nv_global_pci_cap.num_pf_msix_supported==1
valid_bit: num_pf_msix_valid
max_val: $nv_global_pci_cap.max_num_pf_msix
rule:
($nv_global_pci_cap.max_total_msix_valid==0)||($nv_global_pci_cap.max_total_msix==0)||(($num_pfs * ($num_pf_msix + $total_vfs * $num_vf_msix))<=$nv_global_pci_cap.max_total_msix)


name: max_acc_outstanding_read_byte_supported
tlv_name: nv_global_pci_cap
offset: 0x0.17
size: 0x0.1
type: BOOL
description:
When set, maximal accumulated outstanding read bytes can be \;limited by GLOBAL_PCI_CONF_2 max_acc_outstand\;ing_read_byte.


name: vf_nodnic_supported
tlv_name: nv_global_pci_cap
offset: 0x0.22
size: 0x0.1
type: BOOL
description:
When TRUE, the device supports enabling a VF to have VSC \;Gateway exposed through PCI, and may access the NODNIC ini\;tialization segment.


name: pf_bar_size_supported
tlv_name: nv_global_pci_cap
offset: 0x0.24
size: 0x0.1
type: BOOL
description:
When set, the log_pf_uar_bar_size field is configurable and the \;max_log_pf_uar_bar_size field is valid.


name: vf_bar_size_supported
tlv_name: nv_global_pci_cap
offset: 0x0.25
size: 0x0.1
type: BOOL
description:
When set, the log_vf_uar_bar_size field is configurable and the \;max_log_vf_uar_bar_size field is valid.


name: max_total_bar_valid
tlv_name: nv_global_pci_cap
offset: 0x0.29
size: 0x0.1
type: BOOL
description:
When set, the NIC will only respect an NV_GLOBAL_PCI_\;CONF TLV if the total bar size required for all PFs and VFs is \;lower or equal to the number specified in the max_total_bar field \;below.


name: max_total_msix_valid
tlv_name: nv_global_pci_cap
offset: 0x0.30
size: 0x0.1
type: BOOL
description:
When set, the NIC will only respect NV_GLOBAL_PCI_CONF \;TLV if the total MSIX required for all PFs and VFs is lower or \;equal to the number specified in the max_total_msix field below.


name: max_vfs_per_pf_valid
tlv_name: nv_global_pci_cap
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When set, the NIC will only respect NV_GLOBAL_PCI_CONF \;TLV if its total_vfs parameter is lower than or equal to the value \;of the max_vfs_per_pf field below.


name: max_total_bar
tlv_name: nv_global_pci_cap
offset: 0x10.0
size: 0x4.0
type: UNSIGNED
description:
Maximum total of the MMIO space for all PFs and VFs com\;bined, in megabytes.\;Note: if the number of PF or VF per port is not a power of 2, this \;parameter will also not be a power of 2.


name: log_max_payload_size
tlv_name: nv_tpt_conf
offset: 0x0.0
size: 0x0.4
type: ENUM
textual_values: AUTOMATIC=0x0,_4KB=0xc
mlxconfig_name: INT_LOG_MAX_PAYLOAD_SIZE
dependency: ignore_dependency
description:
Sets the PCIe burst size for the NIC internal Translation \;and Protection (TPT) mechanism.\;0x0: AUTOMATIC\;0xC: _4KB


name: pcie_credit_token_timeout
tlv_name: nv_global_pci_conf_2
offset: 0x0.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: PCIE_CREDIT_TOKEN_TIMEOUT
dependency: $nv_global_pci_cap.pcie_credit_token_timeout_supported == 1
description:
PCIe credit timeout. In case a pending transaction has no credits \;longer than this timeout value, buffered transactions will be \;dropped. Value is given in milliseconds in the range of 10 to \;4,000. \;Value 0x0 indicates the device will adjust the timeout automati\;cally.\;Value 0xffff disables the feature.\;


name: max_acc_outstanding_read_byte
tlv_name: nv_global_pci_conf_2
offset: 0x0.16
size: 0x0.16
type: UNSIGNED
mlxconfig_name: MAX_ACC_OUT_READ
description:
Maximum accumulated outstanding Read requests bytes. Value is \;given in units of 1K bytes.\;The limit is applied for each PCI bus link individually.\;Value 0x0 indicates the use of device defaults.\;Configuration is available only when NV_PCI_\;CONF.ADVANCED_PCI_SETTINGS is TRUE.

dependency:
($nv_pci_conf.advanced_pci_settings!=0) && ($nv_global_pci_cap.max_acc_outstanding_read_byte_supported==1)


name: pci_switch_lanes_remapping_en
tlv_name: nv_pci_switch_evb_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: PCI_SW_LANES_REMAPPING_EN
dependency: ignore_dependency
description:
When set allows remapping of the PCI switch lanes to \;slots according to the PCI_SW_LANES_MAPPING \;parameter.


name: pci_switch_lanes_mapping
tlv_name: nv_pci_switch_evb_conf
offset: 0x4.24
size: 0x8.0
type: BINARY
mlxconfig_name: PCI_SW_LANES_MAPPING
description:
Evaluated from the LSB, each bit represents the mapping \;of two PCI lanes to independent PCI buses where a value \;of zero indicates that the corresponding lanes are the first \;lanes of a new bus, and a value of 1 indicates that the cor\;responding lanes belongs to the same bus as the previous \;lanes.\;Examples:\;11111110b => all 16 lanes are mapped to the host. The \;actual bus width is learned dynamically so it may also be \;8 or 4 lanes.\;00000000b => The host bus width is up to 2 lanes and \;there are additional 7 independent buses. \;11101110b => The host bus is up to 8 lanes and there is an \;addition bus of up to 8 lanes.


name: number_of_pci_switch_lanes
tlv_name: nv_pci_switch_evb_cap
offset: 0x0.0
size: 0x0.8
type: UNSIGNED
description:
The number of lanes that can be configured in the PCI \;switch using the PCI_SW_LANES_MAPPING parame\;ter.


name: accurate_scheduler
tlv_name: nv_power_conf
offset: 0x0.24
size: 0x0.1
type: BOOL
mlxconfig_name: ACCURATE_TX_SCHEDULER
dependency: ($nv_power_cap.accurate_scheduler_supported==1)
description:
When TRUE, the device will optimize the transmit scheduler \;for high accuracy.\;may hurt performance\;When False, the device defaults will apply for the scheduler.


name: partial_reset
tlv_name: nv_power_conf
offset: 0x0.25
size: 0x0.1
type: BOOL
mlxconfig_name: PARTIAL_RESET_EN
dependency: $nv_power_cap.partial_reset_supported==1
description:
When set, the partial reset flow is enabled. This reset skips on \;resetting GPIOs, loading PLL new parameters and performing \;self-tests. Partial reset will be triggered only if no exceptions \;requiring full reset were detected (for example, if any of the \;boot record"s parameter had changed)


name: sw_recovery_on_error
tlv_name: nv_power_conf
offset: 0x0.28
size: 0x0.1
type: BOOL
mlxconfig_name: SW_RECOVERY_ON_ERRORS
dependency: ($nv_power_cap.sw_recovery_on_error_supported==1)
description:
When set, SW will be instructed to perform a recovery flow \;when health buffer reports an error. \;


name: reset_with_host_on_errors
tlv_name: nv_power_conf
offset: 0x0.29
size: 0x0.1
type: BOOL
mlxconfig_name: RESET_WITH_HOST_ON_ERRORS
dependency: ($nv_power_cap.reset_with_host_on_errors_supported==1)
description:
When set, host reset will trigger a device reset, if the device has \;previously detected fatal errors.\;


name: slot_power_limiter_dis
tlv_name: nv_power_conf
offset: 0x0.30
size: 0x0.1
type: BOOL
mlxconfig_name: DISABLE_SLOT_POWER_LIMITER
dependency: ($nv_power_conf.advanced_power_settings_en==1)&&($nv_power_cap.slot_power_limiter_supported==1)
description:
When cleared, the device is not allowed to consume more than \;25W from the PCIe power rails, unless a PCI slot power limit \;message statesthat a new power limit is received.\;When set, the slot power limiter is disabled, and the device is \;allowed to consume more than 25W from the PCIe power rails.\;Note: if the power limiter is active and there is not enough \;power, the device will shut down the network modules.\;


name: advanced_power_settings_en
tlv_name: nv_power_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: ADVANCED_POWER_SETTINGS
dependency: $nv_power_cap.slot_power_limiter_supported==1
description:
Show/hide additional power settings parameters.\;Warning: Wrong power settings may cause physical damage.\;


name: accurate_scheduler_supported
tlv_name: nv_power_cap
offset: 0x0.24
size: 0x0.1
type: BOOL
description:
When TRUE, the transmit scheduler may be optimized for high \;accuracy by NV_POWER_CONF.accurate_scheduler


name: idle_icmd_sem_lock_threshold
tlv_name: nv_host_sync_conf
offset: 0x0.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: IDLE_ICMD_SEM_LOCK_THRESHOLD
description:
Host will be expelled from VSEC Gateway usage if it \;holds the ICMD Global Semaphore, without issuing any \;ICMD, for a period longer than this threshold. Value is \;given in units of 0.1sec\;Value 0xFFFF indicates this threshold is infinite (dis\;abled)


name: icmd_sem_lock_threshold
tlv_name: nv_host_sync_conf
offset: 0x0.16
size: 0x0.16
type: UNSIGNED
mlxconfig_name: ICMD_SEM_LOCK_THRESHOLD
description:
Host will be expelled from VSEC Gateway usage if it \;holds the ICMD Global Semaphore for a period longer \;than this threshold. Value is given in units of 0.1sec\;Value 0xFFFF indicates this threshold is infinite (dis\;abled)


name: nvme_emu_num_msix
tlv_name: nv_emulation_nvme_conf
offset: 0x14.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: NVME_EMULATION_NUM_MSIX
dependency: ($nv_emulation_nvme_cap.nvme_emu_supported==1)
description:
Number of MSI-X Vectors assigned for each PF/VF of the \;NVME emulation device. Value 0x0 will use device \;defaults


name: nvme_emu_max_total_vf
tlv_name: nv_emulation_nvme_cap
offset: 0x4.0
size: 0x0.16
type: UNSIGNED
description:
Maximal number of PCIe virtual functions (VFs) sup\;ported by the device for each NVME emulation PF.


name: pci_switch
tlv_name: nv_emulation_pci_switch_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: PCI_SWITCH_EMULATION_ENABLE
dependency: ($nv_emulation_pci_switch_cap.pci_switch_supported==1)
description:
When TRUE, the device will expose a PCI switch. All PF \;configurations are applied on the switch downstream \;ports. On such case, each PF will have a different PCI \;device on the emulated switch. This configuration allows \;to expose 0 network PFs toward host


name: virtio_net_emu_enable
tlv_name: nv_emulation_virtio_net_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
description: When set to TRUE, VIRTIO_NET device emulation is \;enabled.
mlxconfig_name: VIRTIO_NET_EMULATION_ENABLE
dependency:
($nv_emulation_virtio_net_cap.virtio_net_emu_supported==1) && ($nv_emulation_pci_switch_cap.pci_switch_supported==1)


name: virtio_net_emu_num_msix
tlv_name: nv_emulation_virtio_net_conf
offset: 0x14.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: VIRTIO_NET_EMULATION_NUM_MSIX
description:
Number of MSI-X Vectors assigned for each PF/VF of the \;VIRTIO_NET emulation device. Value 0x0 will use \;device defaults


name: virtio_net_emu_max_total_vf
tlv_name: nv_emulation_virtio_net_cap
offset: 0x4.0
size: 0x0.16
type: UNSIGNED
description:
Maximal number of PCIe virtual functions (VFs) sup\;ported by the device for each VIRTIO_NET emulation PF.


name: virtio_blk_emu_enable
tlv_name: nv_emulation_virtio_blk_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
description: When set to TRUE, VIRTIO_BLK device emulation is \;enabled.
mlxconfig_name: VIRTIO_BLK_EMULATION_ENABLE
dependency:
($nv_emulation_virtio_blk_cap.virtio_blk_emu_supported==1) && ($nv_emulation_pci_switch_cap.pci_switch_supported==1)


name: virtio_blk_emu_num_msix
tlv_name: nv_emulation_virtio_blk_conf
offset: 0x14.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: VIRTIO_BLK_EMULATION_NUM_MSIX
description:
Number of MSI-X Vectors assigned for each PF/VF of the \;VIRTIO_BLK emulation device. Value 0x0 will use \;device defaults


name: virtio_blk_emu_max_total_vf
tlv_name: nv_emulation_virtio_blk_cap
offset: 0x4.0
size: 0x0.16
type: UNSIGNED
description:
Maximal number of PCIe virtual functions (VFs) sup\;ported by the device for each VIRTIO_BLK emulation \;PF.


name: bus1_speed
tlv_name: nv_global_pci_conf_3
offset: 0x0.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4
mlxconfig_name: PCI_BUS1_RESTRICT_SPEED
dependency: $nv_global_pci_cap_3.bus1_restrict_en == 1
valid_bit: bus1_restrict
max_val: $nv_global_pci_cap_3.bus1_speed_max
description:
See PCI_BUS0_RESTRICT_SPEED\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5


name: bus0_speed
tlv_name: nv_global_pci_conf_3
offset: 0x0.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4
mlxconfig_name: PCI_BUS0_RESTRICT_SPEED
dependency: $nv_global_pci_cap_3.bus0_restrict_en == 1
valid_bit: bus0_restrict
max_val: $nv_global_pci_cap_3.bus0_speed_max
description:
Restricts the PCI speed to be smaller or equal to:\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;Valid when PCI_BUS_RESTRICT is TRUE.


name: bus0_width
tlv_name: nv_global_pci_conf_3
offset: 0x0.28
size: 0x0.3
type: ENUM
textual_values: PCI_X1=0x0,PCI_X2=0x1,PCI_X4=0x2,PCI_X8=0x3,PCI_X16=0x4
mlxconfig_name: PCI_BUS0_RESTRICT_WIDTH
dependency: $nv_global_pci_cap_3.bus0_restrict_en == 1
valid_bit: bus0_restrict
max_val: $nv_global_pci_cap_3.bus0_width_max
description:
Restricts the PCI bus width to be smaller or equal to:\;0x0: PCI_X1\;0x1: PCI_X2\;0x2: PCI_X4\;0x3: PCI_X8\;0x4: PCI_X16\;Valid when PCI_BUS_RESTRICT is TRUE.


name: bus0_restrict
tlv_name: nv_global_pci_conf_3
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: PCI_BUS0_RESTRICT
dependency: $nv_global_pci_cap_3.bus0_restrict_en == 1
description:
When TRUE, PCI bus width, speed and ASPM will be restricted \;according to PCI_BUS_RESTRICT_WIDTH, PCI_BUS_RE\;STRICT_SPEED, PCI_BUS_RESTRICT_ASPM respectively


name: nvia_nvconfig_on_boot
tlv_name: nv_debug_mode
offset: 0x0.0
size: 0x0.1
type: BOOL
description:
Debug only.\;When set, firmware invalidates all NVCONFIG parame\;ters on boot including this parameter.


name: uefi_aip_over_ctrl
tlv_name: nv_rom_ini
offset: 0x0.21
size: 0x0.1
type: BOOL
dependency: ($nv_rom_cap.uefi_proto_over_ctrl==1)
description:
When set to TRUE, UEFI driver should load UEFI AIP protocols \;over the controller. Otherwise, UEFI driver should load UEFI \;AIP protocols over the child. \;Valid if NV_ROM_CAP.uefi_proto_over_ctrl is TRUE


name: uefi_fmp_over_ctrl
tlv_name: nv_rom_ini
offset: 0x0.22
size: 0x0.1
type: BOOL
dependency: ($nv_rom_cap.uefi_proto_over_ctrl==1)
description:
When set to TRUE, UEFI driver should load UEFI FMP proto\;cols over the controller. Otherwise, UEFI driver should load \;UEFI FMP protocols over the child. \;Valid if NV_ROM_CAP.uefi_proto_over_ctrl is TRUE


name: uefi_hii_over_ctrl
tlv_name: nv_rom_ini
offset: 0x0.23
size: 0x0.1
type: BOOL
dependency: ($nv_rom_cap.uefi_proto_over_ctrl==1)
description:
When set to TRUE, UEFI driver should load UEFI HII protocols \;over the controller. Otherwise, UEFI driver should load UEFI HII \;protocols over the child. \;Valid if NV_ROM_CAP.uefi_proto_over_ctrl is TRUE


name: dhcp_user_class
tlv_name: nv_rom_ini
offset: 0x4.24
size: 0x8.0
type: UNSIGNED
description:
DHCP user class option (RFC3004) for Flexboot.\;Octet #1 must be equal for 77d.\;octet #2 - length\;


name: hii_type
tlv_name: nv_rom_ini
offset: 0xC.16
size: 0x0.4
type: ENUM
textual_values: MLNX_DEFAULT=0x0,HPE=0x1,LENOVO=0x2,DELL=0x3,FUJITSU=0x4
description:
Type of vfr type with HII configuration selector:\;0x0: MLNX_DEFAULT\;0x1: HPE\;0x2: LENOVO\;0x3: DELL\;0x4: FUJITSU


name: hii_mriname2
tlv_name: nv_rom_ini
offset: 0xC.20
size: 0x0.1
type: BOOL
description:
Expose MRI_NAME2 field in HII with hard coded value of \;"Mellanox Network Adapter, physical ports $p, Logical ports 1" \;per Lenovo"s HII spec


name: legacy_boot_wo_failover_supported
tlv_name: nv_rom_cap
offset: 0x0.23
size: 0x0.1
type: BOOL
description:
When set to TRUE, FlexBoot supports configuration of boot \;protocol, without failover to another protocol upon failure \;(NV_ROM_BOOT_CONF1.legacy_boot_protocol).


name: flexboot_debug_en
tlv_name: nv_rom_cap
offset: 0x0.29
size: 0x0.1
type: BOOL
description:
When set, Flexboot debug is supported (NV_ROM_FLEX\;BOOT_DEBUG and NV_ROM_DEBUG_LEVEL are appli\;cable)


name: boot_ip_ver
tlv_name: nv_rom_cap
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
This bit is set when flexboot supports configuration of PXE \;boot IP version defined in boot settings ext parameter


name: cqe_compression
tlv_name: nv_sw_offload_conf
offset: 0x0.0
size: 0x0.3
type: ENUM
textual_values: BALANCED=0x0,AGGRESSIVE=0x1
mlxconfig_name: CQE_COMPRESSION
dependency: ignore_dependency
description:
Configure which algorithm should be used by the NIC in \;order to decide when to activate CQE compression based \;on PCIe bus condition. Note that the driver can enable \;compression on a per CQE basis\;0x0: BALANCED\;0x1: AGGRESSIVE


name: esw_fdb_ipv4_ttl_modify_enable
tlv_name: nv_sw_offload_conf
offset: 0x0.6
size: 0x0.1
type: BOOL
mlxconfig_name: ESWITCH_IPV4_TTL_MODIFY_ENABLE
dependency: $nv_sw_offload_cap.esw_fdb_ipv4_ttl_modify_supported == 1
description:
When TRUE, the device will supports e-switch rules mod\;ifying TTL of packets from the uplink to a vport.


name: prio_tag_required_en
tlv_name: nv_sw_offload_conf
offset: 0x0.7
size: 0x0.1
type: BOOL
mlxconfig_name: PRIO_TAG_REQUIRED_EN
dependency: $nv_sw_offload_cap.prio_tag_required_supported == 1
description:
When set to TRUE, the system requires to always have \;prio tag on the network. SW of e-Switch manager should \;set the required flow table rules to ensure that. This field is \;supported only when NV_SW_OFFLOAD_CAP.pri\;o_tag_required==1 and is reported in HCA_CAP.pri\;o_tag_required.


name: pci_atomic_mode
tlv_name: nv_sw_offload_conf
offset: 0x0.12
size: 0x0.3
type: ENUM
mlxconfig_name: PCI_ATOMIC_MODE
dependency: ignore_dependency
description:
PCI Atomic mode.\;0x0: PCI_ATOMIC_DISABLED_EXT_ATOMIC_EN\;ABLED\;0x1: PCI_ATOMICS_ENABLED_EXT_ATOMICS_EN\;ABLED_SERIALIZED - Atomic serialization will guar\;antee atomicity for multiple accesses to the same address\;0x2: PCI_ATOMICS_ENABLED_EXT_ATOMICS_\;DISABLED\;0x3: PCI_ATOMICS_ENABLED_EXT_ATOMICS_EN\;ABLED_NONCOHERENT \;0x4: PCI_ATOMICS_ENABLED_EXT_ATOMICS_EN\;ABLED\;

textual_values:
PCI_ATOMIC_DISABLED_EXT_ATOMIC_ENABLED=0x0,PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED_SERIALIZED=0x1,PCI_ATOMICS_ENABLED_EXT_ATOMICS_DISABLED=0x2,PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED_NONCOHERENT=0x3,PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED=0x4


name: lro_log_timeout0
tlv_name: nv_sw_offload_conf
offset: 0x4.0
size: 0x0.4
type: UNSIGNED
mlxconfig_name: LRO_LOG_TIMEOUT0
dependency: ignore_dependency
description:
Log2 of Large Receive Offload (LRO) timeout #0, in \;microseconds. Driver can select one of the 4 configured \;LRO timeouts on a per Qp basis in run-time (lro_time\;out_period_usecs field of the TIR context)


name: lro_log_timeout1
tlv_name: nv_sw_offload_conf
offset: 0x4.4
size: 0x0.4
type: UNSIGNED
mlxconfig_name: LRO_LOG_TIMEOUT1
dependency: ignore_dependency
description:
Log2 of Large Receive Offload (LRO) timeout #1, in \;microseconds. Driver can select one of the 4 configured \;LRO timeouts on a per Qp basis in run-time (lro_time\;out_period_usecs field of the TIR context)


name: lro_log_timeout2
tlv_name: nv_sw_offload_conf
offset: 0x4.8
size: 0x0.4
type: UNSIGNED
mlxconfig_name: LRO_LOG_TIMEOUT2
dependency: ignore_dependency
description:
Log2 of Large Receive Offload (LRO) timeout #2, in \;microseconds. Driver can select one of the 4 configured \;LRO timeouts on a per Qp basis in run-time (lro_time\;out_period_usecs field of the TIR context)


name: lro_log_timeout3
tlv_name: nv_sw_offload_conf
offset: 0x4.12
size: 0x0.4
type: UNSIGNED
mlxconfig_name: LRO_LOG_TIMEOUT3
dependency: ignore_dependency
description:
Log2 of Large Receive Offload (LRO) timeout #3, in \;microseconds. Driver can select one of the 4 configured \;LRO timeouts on a per Qp basis in run-time (lro_time\;out_period_usecs field of the TIR context)


name: log_tx_psn_win
tlv_name: nv_sw_offload_conf
offset: 0x4.16
size: 0x0.6
type: UNSIGNED
mlxconfig_name: LOG_TX_PSN_WINDOW
dependency: $nv_sw_offload_cap.tx_psn_win_supported == 1
min_val: 0
max_val: 63
description:
Log2 of the transmission PSN window for QPs with Con\;nected Transport Service (RC, DC, XRC).\;Value 0x0 indicates device defaults\;Value 0x3F indicates device maximal supported value\;Values exceeding the device capabilities will be consid\;ered as the device maximal supported value as well.


name: log_max_outstanding_wqe
tlv_name: nv_sw_offload_conf
offset: 0x4.24
size: 0x0.5
type: UNSIGNED
mlxconfig_name: LOG_MAX_OUTSTANDING_WQE
dependency: $nv_sw_offload_cap.max_outstanding_wqe_supported == 1
min_val: 0
max_val: 31
description:
Log2 of the maximal amount of outstanding (uncom\;pleted) WQEs a single Transmit Work Queue may hold. \;Additional WQEs will be delayed until some of the out\;standing WQEs are completed.\;Value 0x0 indicates device default.\;Value 0x1F indicates device maximal supported value


name: max_outstanding_wqe_supported
tlv_name: nv_sw_offload_cap
offset: 0x0.20
size: 0x0.1
type: BOOL
description:
When TRUE, the maximal number of outstanding WQEs \;for a single Transmit Work Queue can be configured using \;in NV_SW_OFFLOAD_CONFIG


name: vector_calc_disable_supported
tlv_name: nv_sw_offload_cap
offset: 0x0.21
size: 0x0.1
type: BOOL
description:
When TRUE, Vector Calc operations can be disabled \;using vector_calc_disable on NV_SW_OFFLOAD_\;CONFIG


name: esw_fdb_ipv4_ttl_modify_supported
tlv_name: nv_sw_offload_cap
offset: 0x0.23
size: 0x0.1
type: BOOL
description:
When set to TRUE, the device supports enabling e-switch \;rules that modify TTL of packets from the uplink to a \;vport, using ESWITCH_IPV4_TTL_MODIFY_EN\;ABLE.


name: pci_atomics_enabled_ext_atomics_enabled_serialized
tlv_name: nv_sw_offload_cap
offset: 0x0.25
size: 0x0.1
type: BOOL
description:
When set, NV_HCA_CONF.pci_atomic_mode supports \;PCI_ATOMICS_ENABLED_EXT_ATOMICS_EN\;ABLED_SERIALIZED mode.


name: pci_atomics_enabled_ext_atomics_enabled_nocoherent
tlv_name: nv_sw_offload_cap
offset: 0x0.27
size: 0x0.1
type: BOOL
description:
When set, NV_HCA_CONF.pci_atomic_mode supports \;PCI_ATOMICS_ENABLED_EXT_ATOMICS_EN\;ABLED_NONCOHERENT mode.


name: erase_lower_priority
tlv_name: nv_file_id_mlnx
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When set, installation of the file will erase all NVCONFIG \;parameters that are at lower priority. If the file priority is \;MLNX, installation of the file will not copy any TLVs from \;the current NVDAT partition. If the file priority is VEN\;DOR_NVCONF, the installation of the file will only copy \;MLNX level TLVs.


name: year
tlv_name: nv_file_id_mlnx
offset: 0x8.16
size: 0x0.16
type: BINARY
description:
year - 4 packed BCD. Note: If year is zero, FW may copy \;the signature time to this TLV before copying it to flash, so \;the NVCONFIG component will have a date&time prop\;erty.


name: year
tlv_name: nv_file_id_vendor
offset: 0x8.16
size: 0x0.16
type: BINARY
description:
year - 4 packed BCD. Note: If year is zero, FW may copy \;the signature time to this TLV before copying it to flash , so \;the NVCONFIG component will have a date&time prop\;erty.


name: image_bank
tlv_name: nv_fpga_data
offset: 0x0.30
size: 0x0.2
type: UNSIGNED
description:
Select which FPGA Image to load. \;0x0: FACTORY_IMAGE - Factory-default Image\;0x1: USER_IMAGE_1 - User configured Image #1\;Other - Reserved\;


name: bus0_speed_max
tlv_name: nv_global_pci_cap_3
offset: 0x0.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4
description:
Maximal supported PCI speed width for restriction\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5


name: bus0_width_max
tlv_name: nv_global_pci_cap_3
offset: 0x0.28
size: 0x0.3
type: ENUM
textual_values: PCI_X1=0x0,PCI_X2=0x1,PCI_X4=0x2,PCI_X8=0x3,PCI_X16=0x4
description:
Maximal supported PCI bus width for restriction\;0x0: PCI_X1\;0x1: PCI_X2\;0x2: PCI_X4\;0x3: PCI_X8\;0x4: PCI_X16


name: bus0_restrict_en
tlv_name: nv_global_pci_cap_3
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When TRUE, PCI bus width, speed and ASPM can be restricted \;according to PCI_BUS_RESTRICT_WIDTH, PCI_BUS_RE\;STRICT_SPEED, PCI_BUS_RESTRICT_ASPM respectively


name: ece_disable_mask
tlv_name: nv_global_mask
offset: 0x0.0
size: 0x4.0
type: BINARY
description:
Enhanced Connection Establishment disable mask. Each \;bit set to 1 will cause the matching bit in ECE to be dis\;abled in ECE negotiation.


name: tls_optimize
tlv_name: nv_performance_tuning_conf
offset: 0x0.23
size: 0x0.1
type: BOOL
mlxconfig_name: TLS_OPTIMIZE
dependency: $nv_performance_tuning_cap.tls_optimize_supported == 1
description:
When TRUE, the device will optimize processing for TLS \;operations.\;\;When FALSE, device defaults will apply for TLS process\;ing.


name: log_sched_burst
tlv_name: nv_performance_tuning_conf
offset: 0x0.24
size: 0x0.5
type: UNSIGNED
mlxconfig_name: TX_SCHEDULER_BURST
dependency: $nv_performance_tuning_cap.sched_burst_supported == 1
min_val: 0
max_val: 31
description:
Log (base2) of the transmission scheduler default burst \;size, given in bytes, Value 0x0 indicates using device \;defaults.


name: ztt_enable
tlv_name: nv_performance_tuning_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: ZERO_TOUCH_TUNING_ENABLE
dependency: ($nv_performance_tuning_cap.ztt_supported==1)
description:
when TRUE, Zero Touch Tuning routine will automati\;cally tune device registers in order to achieve the maxi\;mum performance


name: tls_optimize_supported
tlv_name: nv_performance_tuning_cap
offset: 0x0.29
size: 0x0.1
type: BOOL
description:
When TRUE, TLS performance optimization can be con\;figured using NV_PERFORMANCE_TUNING_\;CONF.tls_optimize


name: sched_burst_supported
tlv_name: nv_performance_tuning_cap
offset: 0x0.30
size: 0x0.1
type: BOOL
description:
When TRUE, the transmit scheduler default burst size can \;be modified by NV_PERFORMANCE_TUNING_\;CONF.log_sched_burst


name: algo_user0_enable
tlv_name: nv_global_roce_cc_conf
offset: 0x0.8
size: 0x0.1
type: BOOL
mlxconfig_name: ROCE_CC_USER0_ALGO_ENABLE
dependency: ($nv_global_roce_cc_cap.algo_user0_supported==1) && ($nv_prog_cc.user_cc_en==1)
valid_bit: algo_select_valid
description:
When TRUE, RoCE CC user-defined algorithm 0 is \;enabled\;Valid only if ROCE_CC_ALGO_SELECT_VALID is \;TRUE


name: preferred_algo
tlv_name: nv_global_roce_cc_conf
offset: 0x0.16
size: 0x0.4
type: ENUM
textual_values: TIMELY=0x0,HPCC=0x1,DC2QCN=0x2,USER0=0x6
mlxconfig_name: ROCE_CC_PREFERRED_ALGO
dependency: ($nv_prog_cc.user_cc_en==1)
valid_bit: algo_select_valid
description:
Indicates the preferred CC algorithm when multiple are \;supported by the two ends of the connection\;0x0: TIMELY\;0x1: HPCC\;0x2: DC2QCN\;0x6: USER0\;other values are reserved.\;Valid only if ROCE_CC_ALGO_SELECT_VALID is \;TRUE

rule:
($nv_global_roce_cc_cap.algo_timely_supported==1 && $preferred_algo==0) || ($nv_global_roce_cc_cap.algo_hpcc_supported==1 && $preferred_algo==1) || ($nv_global_roce_cc_cap.algo_dc2qcn_supported==1 && $preferred_algo==2) || ($nv_global_roce_cc_cap.algo_user0_supported==1 && $preferred_algo==6)


name: algo_select_valid
tlv_name: nv_global_roce_cc_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: ROCE_CC_ALGO_SELECT_VALID
dependency: ($nv_prog_cc.user_cc_en==1)
description:
When TRUE, RoCE CC algorithm will be selected based \;on ROCE_CC_PREFERRED_ALGO and \;ROCE_CC_*_ALGO_ENABLE.\;When FALSE, the RoCE CC algorithm will be selected \;based on device defaults.


name: algo_timely_supported
tlv_name: nv_global_roce_cc_cap
offset: 0x0.0
size: 0x0.1
type: BOOL
description:
When TRUE, RoCE CC algorithm TIMELY is supported, \;and may be enabled using NV_GLOBAL_ROCE_CC_\;CONF


name: algo_dc2qcn_supported
tlv_name: nv_global_roce_cc_cap
offset: 0x0.2
size: 0x0.1
type: BOOL
description:
When TRUE, RoCE CC algorithm DC2QCN is sup\;ported, and may be enabled using NV_GLOBAL_RO\;CE_CC_CONF


name: algo_user0_supported
tlv_name: nv_global_roce_cc_cap
offset: 0x0.8
size: 0x0.1
type: BOOL
description:
When TRUE, RoCE CC user-defined algorithm 0 is sup\;ported, and may be enabled using NV_GLOBAL_RO\;CE_CC_CONF


name: hp_7kd_en
tlv_name: nv_enclosure_info
offset: 0x0.0
size: 0x0.1
type: BOOL
description:
When this bit is set to 1, the NIC PHY should apply PHY \;calibration according to the data specified in the following \;fields


name: current_cfg_method
tlv_name: nv_current_configurator
offset: 0x0.0
size: 0x0.8
type: ENUM
description:
Parameter from "HP ASN1 Data Structure Specification \;v2.8.6.asn"\;0x0: E_NONE - default config\;0x1: OS - O/S making cfg changes in the absences of any \;other Mgmt Util (command interface)\;0x2: E_VENDOR_SPEC - e.g. Vendor"s Option ROM, \;NPAR, O/S Cfg Utils (FW writes this TLV when a TLV is \;written from mlxconfig, that is when NVDA write for any \;TLV is coming from the ICMD gateway without a UEFI \;or flexboot "writer-ID").\;0x3: E_HP_OTHER - (when an extern-DCi-mgmt param\;eter with value e-None is arriving from the BMC ASN.1 \;API)\;0x4: E_VC_CLP - Driver or F/W detects HPE Classic C-\;Class SM-CLP\;0x5: E_HP_CNU - Driver or F/W detects HPE"s Con\;verged Network Utility (when an extern-DCi-mgmt \;parameter with value <to-be-defined-by-HP> is arriving \;from the BMC ASN.1 API)\;0x6: E_HP_ONEVIEW - If manage-via-DCi value equals \;to HPE-OneView(6) in BaseDev-Cfg-Now is coming \;from the BMC ASN.1 API\;0x7: E_UEFI_HII - UEFI Option ROM executing

textual_values:
E_NONE=0x0,OS=0x1,E_VENDOR_SPEC=0x2,E_HP_OTHER=0x3,E_VC_CLP=0x4,E_HP_CNU=0x5,E_HP_ONEVIEW=0x6,E_UEFI_HII=0x7


name: time_synced
tlv_name: nv_invalidate_all_timestamp
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When set, the time field represents the number of micro\;seconds passed since 1/1/1970.\;Otherwise, time is the number of microseconds passed \;since the NIC boot (uptime)


name: ocsd_en
tlv_name: nv_rom_ocsd_ocbb
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
Enable HP on-chip temperature monitoring (OCSD) and \;Active Health Systems support via FW (OCBB) reporting.


name: default_link_type
tlv_name: nv_vpi_link_type
offset: 0x0.2
size: 0x0.2
type: ENUM
textual_values: IB=0x1,ETH=0x2
mlxconfig_name: LINK_TYPE_P1
dependency: ignore_dependency
description:
Select the link type (Ethernet or Infiniband) for the port\;0x1: IB - Infiniband\;0x2: ETH - Ethernet


name: clamp_tgt_rate_after_time_inc
tlv_name: nv_roce_cc_ecn
offset: 0x0.30
size: 0x0.1
type: BOOL
mlxconfig_name: CLAMP_TGT_RATE_AFTER_TIME_INC_P1
dependency: ignore_dependency
description:
When receiving a CNP, the target rate should be updated if \;the transmission rate was increased due to the timer, and \;not only due to the byte counter


name: rpg_threshold
tlv_name: nv_roce_cc_ecn
offset: 0xC.0
size: 0x0.5
type: UNSIGNED
mlxconfig_name: RPG_THRESHOLD_P1
dependency: ignore_dependency
description:
The number of times rpByteStage or rpTimeStage can \;count before the RP rate control state machine advances \;states.


name: rpg_max_rate
tlv_name: nv_roce_cc_ecn
offset: 0x10.0
size: 0x4.0
type: UNSIGNED
mlxconfig_name: RPG_MAX_RATE_P1
dependency: ignore_dependency
description:
The maximum rate, in Mbits per second, at which an RP \;can transmit. Once this limit is reached, the RP rate lim\;ited is released and the flow is not rate limited any more \;(0=Full Port Speed).


name: rpg_gd
tlv_name: nv_roce_cc_ecn
offset: 0x1C.0
size: 0x0.4
type: UNSIGNED
mlxconfig_name: RPG_GD_P1
dependency: ignore_dependency
description:
If a CNP is received, the flow rate is reduced at the begin\;ning of the next rate_reduce_monitor_period interval to \;(1-Alpha/Gd)*CurrentRate. rpg_gd is given as log2(Gd), \;where Gd may only be powers of 2.


name: rpg_min_dec_fac
tlv_name: nv_roce_cc_ecn
offset: 0x20.0
size: 0x0.8
type: UNSIGNED
mlxconfig_name: RPG_MIN_DEC_FAC_P1
dependency: ignore_dependency
min_val: 1
max_val: 100
description:
The minimum factor by which the current transmit rate \;can be changed when processing a CNP. Value is given as \;a percentage (1-100).


name: rate_to_set_on_first_cnp
tlv_name: nv_roce_cc_ecn
offset: 0x28.0
size: 0x0.17
type: UNSIGNED
mlxconfig_name: RATE_TO_SET_ON_FIRST_CNP_P1
dependency: ignore_dependency
description:
The rate that is set for the flow when a rate limiter is allo\;cated to it upon first CNP received, in Mbps (=Full Port \;Speed).


name: dce_tcp_g
tlv_name: nv_roce_cc_ecn
offset: 0x2C.0
size: 0x0.10
type: UNSIGNED
mlxconfig_name: DCE_TCP_G_P1
dependency: ignore_dependency
min_val: 1
description:
Used to update the congestion estimator (alpha) once \;every dce_tcp_rtt microseconds, according to the equa\;tion:\;Alpha = (cnp_received * dceTcpG) + (1 - dceTcpG) * \;alpha .\;dceTcpG is divided by 2^10.\;cnp_received is set to one if a CNP was received for this \;flow during period since the previous update and the cur\;rent update


name: rate_reduce_monitor_period
tlv_name: nv_roce_cc_ecn
offset: 0x34.0
size: 0x0.17
type: UNSIGNED
mlxconfig_name: RATE_REDUCE_MONITOR_PERIOD_P1
dependency: ignore_dependency
min_val: 1
description:
The minimum time between 2 consecutive rate reductions \;for a single flow. Rate reduction will occur only if a CNP \;is received during the relevant time interval.


name: initial_alpha_value
tlv_name: nv_roce_cc_ecn
offset: 0x38.0
size: 0x0.10
type: UNSIGNED
mlxconfig_name: INITIAL_ALPHA_VALUE_P1
dependency: ignore_dependency
description:
The initial value of alpha to use when receiving the first \;CNP for a flow. Expressed in a fixed point fraction of \;2^10.


name: cnp_prio_mode
tlv_name: nv_roce_cc_ecn
offset: 0x40.3
size: 0x0.1
type: BOOL
mlxconfig_name: CNP_RES_PRIO_MODE_P1
description:
If TRUE, CNP packets for this port contain priority from a \;received request. If FALSE, CNP responses use value set \;by CNP_802P_PRIO.


name: rpg_threshold
tlv_name: nv_roce_cc_qcn
offset: 0xC.0
size: 0x0.5
type: UNSIGNED
description:
The number of times rpByteStage or rpTimeStage can \;count before the RP rate control state machine advances \;states.\;


name: rpg_max_rate
tlv_name: nv_roce_cc_qcn
offset: 0x10.0
size: 0x4.0
type: UNSIGNED
description:
The maximum rate, in Mbits per second, at which an RP \;can transmit. Once this limit is reached, the RP rate lim\;ited is released and the flow stops being limited (0=Full \;Port Speed)\;


name: rpg_gd
tlv_name: nv_roce_cc_qcn
offset: 0x1C.0
size: 0x0.4
type: UNSIGNED
description:
When a CNP is received, the flow rate is reduced at the \;beginning of the next rate_reduce_monitor_period inter\;val to (1-Alpha/Gd)*CurrentRate. rpg_gd is given as \;log2(Gd), where Gd may only be powers of 2.\;


name: rpg_min_dec_fac
tlv_name: nv_roce_cc_qcn
offset: 0x20.0
size: 0x0.8
type: UNSIGNED
description:
The minimum factor by which the current transmit rate \;can be changed when processing a CNP. Value is given as \;a percentage (1-100).\;


name: lldp_nb_rx_mode
tlv_name: nv_lldp_nb_conf
offset: 0x0.28
size: 0x0.2
type: ENUM
textual_values: OFF=0x0,MANDATORY=0x1,ALL=0x2
mlxconfig_name: LLDP_NB_RX_MODE_P1
dependency: $nv_lldp_nb_cap.lldp_nb_rx_cap!=0
max_val: $nv_lldp_nb_cap.lldp_nb_rx_cap
description:
Enable the internal LLDP client, and define which TLV it \;will process.\;0x0: OFF - Doesnot listen to incoming LLDP BPDU \;(incoming LLDP frames will be routed to the host)\;0x1: MANDATORY - Listen to incoming LLDP frames, \;store only the mandatory LLDP BPDUs (1..3)\;0x2: ALL - Receive and store all incoming LLDP BPDUs


name: lldp_nb_tx_mode
tlv_name: nv_lldp_nb_conf
offset: 0x0.30
size: 0x0.2
type: ENUM
textual_values: OFF=0x0,MANDATORY=0x1,ALL=0x2
mlxconfig_name: LLDP_NB_TX_MODE_P1
dependency: $nv_lldp_nb_cap.lldp_nb_tx_cap!=0
max_val: $nv_lldp_nb_cap.lldp_nb_tx_cap
description:
Select which LLDP TLV will be generated by the NIC\;0x0: OFF - NIC internal LLDP client will not send LLDP \;frames \;0x1: MANDATORY - Transmits only mandatory LLDP \;BPDU (ChassisID, PortID & TTL)\;0x2: ALL - Transmits optional LLDP BPDU if configured


name: lldp_nb_rx_cap
tlv_name: nv_lldp_nb_cap
offset: 0x0.28
size: 0x0.2
type: ENUM
textual_values: NA=0x0,MANDATORY=0x1,ALL=0x2
description:
0x0: NA - Reception and storing of LLDP frames is not \;supported (incoming frames will be forwarded to the host)\;0x1: MANDATORY - The client can only store received  \;mandatory LLDP-TLVs \;0x2: ALL - The client can receive and store incoming \;LLDP TLVs


name: lldp_nb_tx_cap
tlv_name: nv_lldp_nb_cap
offset: 0x0.30
size: 0x0.2
type: ENUM
textual_values: NA=0x0,MANDATORY=0x1,ALL=0x2,reserved=0x3
description:
0x0: NA - LLDP transmission not supported \;0x1: MANDATORY - The LLDP client only support \;sending  the mandatory LLDP NB TLVs (ChassisID, Por\;tID & TTL)\;0x2: ALL - The LLDP client support sending mandatory \;and optional TLVs \;0x3: reserved


name: max_num_of_tx_optional_lldp_tlv
tlv_name: nv_lldp_nb_cap
offset: 0x8.0
size: 0x0.7
type: UNSIGNED
description:
The maximum number of optional LLDP TLVs that are \;supported by the firmware. The firmware is searching for \;LLDP NB TLV to send from type 0x110 to type (0x110 + \;this field)\;Default: 16


name: keep_eth_link_up
tlv_name: nv_keep_link_up
offset: 0x0.0
size: 0x0.1
type: BOOL
mlxconfig_name: KEEP_ETH_LINK_UP_P1
dependency: ignore_dependency
description:
When set, the NIC keeps the link up as long as the server is \;not in standby mode (Ethernet only).\;


name: keep_ib_link_up
tlv_name: nv_keep_link_up
offset: 0x0.1
size: 0x0.1
type: BOOL
mlxconfig_name: KEEP_IB_LINK_UP_P1
description:
When set, the NIC keeps the link up as long as the server is \;not in standby mode (InfiniBand only).


name: keep_link_up_on_boot
tlv_name: nv_keep_link_up
offset: 0x0.2
size: 0x0.1
type: BOOL
mlxconfig_name: KEEP_LINK_UP_ON_BOOT_P1
description:
When set, the NIC keeps the link up as long as the server is \;not in standby mode and a driver is not initialized.


name: keep_link_up_on_standby
tlv_name: nv_keep_link_up
offset: 0x0.3
size: 0x0.1
type: BOOL
mlxconfig_name: KEEP_LINK_UP_ON_STANDBY_P1
description:
When set, the NIC keeps the link up from power-up until \;the server is turned on, and when the server is in standby\;mode (PCI L2/3 state). \;Note: The link will be kept up only if the server can provide \;enough power during standby (via PCI rails or AUX \;power).


name: do_not_clear_port_stats
tlv_name: nv_keep_link_up
offset: 0x0.4
size: 0x0.1
type: BOOL
mlxconfig_name: DO_NOT_CLEAR_PORT_STATS_P1
description:
When set, the port statistic counters are not cleared on first \;host init. When cleared the port statistics are cleared on first \;host init


name: num_of_vl
tlv_name: nv_qos_conf
offset: 0x0.0
size: 0x0.4
type: ENUM
textual_values: _1_VL=0x1,_2_VLs=0x2,_4_VLs=0x3,_8_VLs=0x4,_15_VLs=0x5
mlxconfig_name: NUM_OF_VL_P1
dependency: ignore_dependency
min_val: 1
max_val: $nv_qos_cap.max_num_of_vl
description:
Number of Infiniband Virtual Lanes for this port\;0x1: _1_VL - VL0 only\;0x2: _2_VLs - VL0, VL1\;0x3: _4_VLs - VL0..VL3\;0x4: _8_VLs - VL0..VL7\;0x5: _15_VLs --VL0, VL14 (VL15 is always present for \;MADs)


name: num_of_tc
tlv_name: nv_qos_conf
offset: 0x0.4
size: 0x0.4
type: ENUM
textual_values: _8_TCs=0x0,_1_TC=0x1,_2_TCs=0x2,_3_TCs=0x3,_4_TCs=0x4,_5_TCs=0x5,_6_TCs=0x6,_7_TCs=0x7
mlxconfig_name: NUM_OF_TC_P1
dependency: ignore_dependency
min_val: ($nv_qos_cap.max_num_of_tc==0)?0:1
max_val: ($nv_qos_cap.max_num_of_tc==0)?7:$nv_qos_cap.max_num_of_tc
description:
Number of traffic classes, when DCB-X is enabled, this is \;the maximum number of TC that can negotiate with the \;remote peer. \;0x0: _8_TCs\;0x1: _1_TC\;0x2: _2_TCs\;0x3: _3_TCs\;0x4: _4_TCs\;0x5: _5_TCs\;0x6: _6_TCs\;0x7: _7_TCs


name: num_of_pfc
tlv_name: nv_qos_conf
offset: 0x0.8
size: 0x0.4
type: UNSIGNED
mlxconfig_name: NUM_OF_PFC_P1
dependency: ignore_dependency
max_val: $nv_qos_cap.max_num_pfc
description:
Number of IEEE priorities that may simultaneously sup\;port flow control. \; (See pfc_cap_admin DCBX_PARAM Register)


name: log_vl15_buffer_size
tlv_name: nv_qos_conf
offset: 0x0.12
size: 0x0.4
type: UNSIGNED
mlxconfig_name: VL15_BUFFER_SIZE_P1
dependency: $nv_qos_cap.log_max_vl15_buffer_size!=0
max_val: $nv_qos_cap.log_max_vl15_buffer_size
description:
Log (base 2) of the VL15 receive port buffer, given in \;units of 512B. Value 0x0 indicates device defaults.\;Valid only for Infiniband links.


name: max_num_of_vl
tlv_name: nv_qos_cap
offset: 0x0.0
size: 0x0.4
type: ENUM
textual_values: _1_VL=0x1,_2_VLs=0x2,_4_VLs=0x3,_8_VLs=0x4,_15_VLs=0x5
description:
Maximum number of VLs supported by the HBA.\;0x1: _1_VL - VL0 only\;0x2: _2_VLs - VL0, VL1\;0x3: _4_VLs - VL0..VL3\;0x4: _8_VLs - VL0..VL7\;0x5: _15_VLs -- VL0..VL14 (VL15 is always present for \;MADs)


name: log_max_vl15_buffer_size
tlv_name: nv_qos_cap
offset: 0x0.12
size: 0x0.4
type: UNSIGNED
description:
Maximum value supported for NV_QOS_\;CONF.log_vl15_buffer_size. Value 0x0 indicates \;NV_QOS_CONF.log_vl15_buffer_size is not supported.


name: duplicated_mac_action_mode
tlv_name: nv_mpfs_conf
offset: 0x0.0
size: 0x0.4
type: ENUM
textual_values: LAST_CFG=0x0,LOAD_BALANCE=0x1
mlxconfig_name: DUP_MAC_ACTION_P1
dependency: ignore_dependency
description:
Defines the forwarding behavior in MPFS for MACs which are \;duplicated in more than one PF.\;0x0: LAST_CFG - last PF which added the MAC will receive \;the traffic.\;0x1: LOAD_BALANCE - MPFS will load-balance ipv4 traffic \;for packets with destination MAC addresses that belong to \;more than one PF between all PFs that have this MAC


name: unknown_uplink_mac_flood
tlv_name: nv_mpfs_conf
offset: 0x0.7
size: 0x0.1
type: BOOL
mlxconfig_name: UNKNOWN_UPLINK_MAC_FLOOD_P1
dependency: $nv_mpfs_cap.unknown_uplink_mac_flood_supported!=0
description:
Defines the forwarding behavior in MPFS for packets arriving \;from the network (uplink) with destination MAC address that \;does not appear in the MPFS FDB.\;When TRUE, these packets are flooded to all local MPFS\;ports.\;When FALSE, these packets are dropped.


name: ib_routing_mode
tlv_name: nv_mpfs_conf
offset: 0x0.31
size: 0x0.1
type: ENUM
textual_values: GID=0x0,LID=0x1
mlxconfig_name: IB_ROUTING_MODE_P1
dependency: $nv_mpfs_cap.ib_routing_mode_supported!=0
description:
Select the routing mode for Infiniband among the PFs (and \;hosts, if applicable)\;0x0: GID - each PF has a unique GID\;0x1: LID - each PF has a unique LID


name: en_wol_magic
tlv_name: nv_wol_cap
offset: 0x0.10
size: 0x0.1
type: BOOL
description:
This bit is set when Wake-On-Lan magic packet is supported for \;this host and port. Note that WOL support mandates a special cir\;cuitry on the NIC.


name: total_sf
tlv_name: nv_pf_pci_conf
offset: 0x0.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: PF_TOTAL_SF
dependency: $nv_global_pci_cap.per_pf_num_sf_supported==1
valid_bit: pf_total_sf_en
description:
The total number of Sub Function partitions (SFs) that can be sup\;ported, for this PF. \;Valid only when PER_PF_NUM_SF is set to TRUE


name: log_sf_bar_size
tlv_name: nv_pf_pci_conf
offset: 0x0.24
size: 0x0.8
type: UNSIGNED
mlxconfig_name: PF_SF_BAR_SIZE
dependency: $nv_global_pci_cap.per_pf_num_sf_supported==1
valid_bit: pf_total_sf_en
description:
Log (base 2) of the BAR size of a single SF, given in KB. Valid \;only when total_sf is non-zero. \;Valid only when PER_PF_SF_VALID is set to TRUE


name: num_pf_msix
tlv_name: nv_pf_pci_conf
offset: 0x4.0
size: 0x0.12
type: UNSIGNED
mlxconfig_name: PF_NUM_PF_MSIX
description:
Number of MSI-X vectors assigned for this PF\;Value 0x0 indicates device defaults.\;Valid only when PER_PF_NUM_MSIX is set to TRUE


name: virtual_guid_en
tlv_name: nv_virt_guid_addr
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When set, the PF will use the address defined in the "virtu\;al_node_guid" instead of the original MAC.


name: pci_data_wr_ordering_mode
tlv_name: nv_hca_conf
offset: 0x0.28
size: 0x0.2
type: ENUM
textual_values: per_mkey=0x0,force_relax=0x1
mlxconfig_name: PCI_WR_ORDERING
dependency: $nv_hca_cap.pci_data_wr_ordering_supported!=0
description:
Controls the PCI ordering attribute for write accesses from the \;device\;0x0: per_mkey - Each MKey may be configured differently for \;Relaxed Ordering\;0x1: force_relax - All MKeys will be set to use Relaxed Ordering \;at creation time\;show this setting only when NV_PCI_CONF. advanced_pci_set\;tings is true.


name: esw_manager
tlv_name: nv_ecpf_conf
offset: 0x0.0
size: 0x0.2
type: ENUM
description: Select who owns the E-switch.\;0x0: EXTERNAL_HOST_PF\;0x1: ECPF
textual_values: EXTERNAL_HOST_PF=0x0,ECPF=0x1
mlxconfig_name: ECPF_ESWITCH_MANAGER
dependency:
($nv_ecpf_cap.esw_manager_ecpf_supported==1) || ($nv_ecpf_cap.esw_manager_external_host_pf_supported==1)

rule:
($esw_manager==0 && $nv_ecpf_cap.esw_manager_external_host_pf_supported==1) || ($esw_manager==1 && $nv_ecpf_cap.esw_manager_ecpf_supported==1)


name: page_supplier
tlv_name: nv_ecpf_conf
offset: 0x0.8
size: 0x0.2
type: ENUM
textual_values: EXTERNAL_HOST_PF=0x0,ECPF=0x1
mlxconfig_name: ECPF_PAGE_SUPPLIER
description:
Select who supplies ICM pages of the external host functions to \;device. \;0x0: EXTERNAL_HOST_PF - External host supplies required \;ICM pages to handle it.\;0x1: ECPF - ECPF supplies required ICM pages to handle the \;external host.\;

dependency:
($nv_ecpf_cap.external_host_page_supplier_ecpf_supported==1) || ($nv_ecpf_cap.external_host_page_supplier_external_host_pf_supported==1)

rule:
($page_supplier==0 && $nv_ecpf_cap.external_host_page_supplier_external_host_pf_supported==1) || ($page_supplier==1 && $nv_ecpf_cap.external_host_page_supplier_ecpf_supported==1)


name: reneg_on_change
tlv_name: nv_external_port_ctrl
offset: 0x0.2
size: 0x0.1
type: BOOL
mlxconfig_name: RENEG_ON_CHANGE
description:
When cleared, a link-down/up sequence from the driver \;(PAOS) triggers re-negotiation of the link speed and \;parameters with the remote peer. When set, a link down/\;up sequence will trigger re-negotiation only if any link \;parameters were changed by a driver since last link nego\;tiation. \;This parameter is applicable when the port_owner param\;eter is set for this PF


name: boot_ip_ver
tlv_name: nv_rom_boot_conf2
offset: 0x0.8
size: 0x0.2
type: ENUM
textual_values: IPv4=0x0,IPv6=0x1,IPv4_IPv6=0x2,IPv6_IPv4=0x3
mlxconfig_name: IP_VER
dependency: $nv_rom_cap.boot_ip_ver!=0
description:
Select which IP protocol version will be used by Flexboot. \;If both are configured, Flexboot will try to boot with the \;2nd protocol only if DHCP parameters for the first proto\;col are not available, or if booting with the first protocol \;has failed.\;0x0: IPv4\;0x1: IPv6\;0x2: IPv4_IPv6\;0x3: IPv6_IPv4\;


name: undi_network_wait
tlv_name: nv_rom_boot_conf2
offset: 0x0.16
size: 0x0.8
type: UNSIGNED
mlxconfig_name: BOOT_UNDI_NETWORK_WAIT
description:
The number of seconds Flexboot waits after issuing a \;UNDI open commands until it starts using the interface.


name: hii_en
tlv_name: nv_rom_uefi_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: UEFI_HII_EN
dependency: $nv_rom_cap.hii_config_en!=0
description:
Enable UEFI/BIOS HII menus for this PCI function. \;Warning: HII menus might be required for fixing and \;debugging of system boot issues.\;


name: debug_log_en
tlv_name: nv_rom_debug_level
offset: 0x0.0
size: 0x0.1
type: BOOL
mlxconfig_name: BOOT_DBG_LOG
dependency: $nv_rom_cap.flexboot_debug_en==1
description:
When set, Flexboot generates debug logs at the levels speci\;fied by the following parameters: BOOT_DBG_LOG_STP, \;BOOT_DBG_LOG_ ROMPREFIX, BOOT_DB\;G_LOG_DHCP, BOOT_DBG_LOG_DHCP6, BOOT_DB\;G_LOG_ARP, BOOT_DBG_LOG_ NEIGHBOR, \;BOOT_DBG_LOG_ NDP, BOOT_DBG_LOG_URI, \;BOOT_DBG_LOG_IB_DRV, BOOT_DB\;G_LOG_DRV_CMD, BOOT_DBG_LOG_DRV_DEV, \;BOOT_DBG_LOG_DRV_PORT, BOOT_DBG_LOG_T\;FTP, BOOT_DBG_LOG_UDP, BOOT_DBG_LOG_TCP, \;BOOT_DBG_LOG_TCPIP, BOOT_DBG_LOG_IP, and \;OOT_DBG_LOG_IPV6.\;


name: stp
tlv_name: nv_rom_debug_level
offset: 0x4.0
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_STP
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot's Spanning Tree Protocol\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: romprefix
tlv_name: nv_rom_debug_level
offset: 0x4.2
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_ROMPREFIX
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot's driver bootstrap code\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: arp
tlv_name: nv_rom_debug_level
offset: 0x4.8
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_ARP
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot's Address resolution Protocol \;(ARP)\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: neighbor
tlv_name: nv_rom_debug_level
offset: 0x4.10
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NEIGHBOR
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot's Neighbor table (which is filled \;by ARP and NDP)\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: ndp
tlv_name: nv_rom_debug_level
offset: 0x4.12
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NDP
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s IPv6 Neighbor Discovery Proto\;col\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: driver
tlv_name: nv_rom_debug_level
offset: 0x4.16
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_DRV
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s driver (init, teardown, poll CQ \;etc) \;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: nodnic
tlv_name: nv_rom_debug_level
offset: 0x4.18
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NDRV
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s NODNIC driver (init, teardown, \;poll CQ etc) \;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: nodnic_cmd
tlv_name: nv_rom_debug_level
offset: 0x4.20
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NDRV_CMD
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s NODNIC Driver interface\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: nodnic_device
tlv_name: nv_rom_debug_level
offset: 0x4.22
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NDRV_DEV
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s NODNIC Driver tear-down and \;bring ups operations.\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: nodnic_port
tlv_name: nv_rom_debug_level
offset: 0x4.24
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NDRV_PORT
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s NODNIC Driver port manage\;ment.\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: driver_settings
tlv_name: nv_rom_debug_level
offset: 0x8.8
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_DRIVER_SETTINGS
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for non volatile configuration management.\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: panic_banner
tlv_name: nv_rom_flexboot_debug
offset: 0x0.29
size: 0x0.2
type: ENUM
textual_values: PRINT=0x0,HALT=0x1,OPEN_SHELL=0x2
description:
Flexboot behavior on critical failure \;0x0: PRINT - print error to screen\;0x1: HALT - freeze system\;0x2: OPEN_SHELL - open ipxe shell


name: uefi_log_severity
tlv_name: nv_rom_uefi_debug_level
offset: 0x0.24
size: 0x0.2
type: ENUM
textual_values: ERROR=0x0,WARNING=0x1,INFO=0x2,DEBUG=0x3
mlxconfig_name: UEFI_LOG_MIN_SEVERITY
dependency: ($nv_rom_uefi_debug_level.uefi_logs!=0)&&($nv_rom_cap.uefi_logs_en==1)
description:
NIC/HBA UEFI expansion ROM\;0x0: ERROR\;0x1: WARNING\;0x2: INFO\;0x3: DEBUG\;Note - Enabling of debug logs for specific modules is possi\;ble after setting the severity to DEBUG.\;


name: uefi_logs
tlv_name: nv_rom_uefi_debug_level
offset: 0x0.28
size: 0x0.4
type: ENUM
textual_values: DISABLED=0x0,STDOUT=0x1,STDERR=0x2
mlxconfig_name: UEFI_LOGS
dependency: ($nv_rom_cap.uefi_logs_en==1)
description:
Select the output device logs generated by the NIC/HBA\;UEFI expansion ROM.\;0x0: DISABLED\;0x1: STDOUT\;0x2: STDERR\;


name: flexboot_banner_timeout
tlv_name: nv_rom_banner_timeout
offset: 0x0.0
size: 0x0.4
type: UNSIGNED
description:
Number of seconds to wait when displaying the timer for \;the boot menu key-press. If set to 0 the boot menu is dis\;abled. The boot menu is only allowed to write values \;between 1 and 15. UEFI and mlxconfig may write 0.


name: legacy_boot_protocol
tlv_name: nv_rom_boot_conf1
offset: 0x0.16
size: 0x0.8
type: ENUM
textual_values: NONE=0x0,PXE=0x1,ISCSI=0x2,PXE_WO_FAIL_ISCSI=0x4,ISCSI_WO_FAIL_PXE=0x5
mlxconfig_name: LEGACY_BOOT_PROTOCOL
description:
Select boot protocol for legacy BIOS expansion ROM \;(Flexboot)\;0x0: NONE - The expansion ROM will not add this PCI PF \;as a boot target during the POST stage.\;0x1: PXE - The expansion ROM will use PXE boot.\;0x2: ISCSI - The expansion ROM will use iSCSI boot.\;0x4: PXE_WO_FAIL_ISCSI - PXE without fail-over to \;ISCSI. Supported when legacy_boot_wo_failover_sup\;ported==1.\;0x5: ISCSI_WO_FAIL_PXE - ISCSI without fail-over to \;PXE.Supported when legacy_boot_wo_failover_sup\;ported==1.


name: boot_retry_count
tlv_name: nv_rom_boot_conf1
offset: 0x0.24
size: 0x0.3
type: ENUM
textual_values: NONE=0x0,_1=0x1,_2=0x2,_3=0x3,_4=0x4,_5=0x5,_6=0x6,UNLIMITED=0x7
mlxconfig_name: BOOT_RETRY_CNT
description:
Number of retries to attempt in case of boot failure (Flex\;Boot)\;0x0: NONE\;0x1: _1\;0x2: _2\;0x3: _3\;0x4: _4\;0x5: _5\;0x6: _6\;0x7: UNLIMITED\;


name: boot_legacy_interrupt_disable
tlv_name: nv_rom_boot_conf1
offset: 0x0.27
size: 0x0.1
type: BOOL
mlxconfig_name: BOOT_INTERRUPT_DIS
dependency: $nv_rom_cap.boot_legacy_interrupt_disable_supported!=0
description:
When set to TRUE, legacy interrupts should not be used for \;receive/transmit indication. Polling should be used instead.\;Supported only if boot_legacy_interrupt_disable_supported \;=TRUE.


name: lacp_dis
tlv_name: nv_rom_boot_conf1
offset: 0x0.29
size: 0x0.1
type: BOOL
mlxconfig_name: BOOT_LACP_DIS
dependency: $nv_rom_cap.lacp_config_en!=0
description:
Disable IEEE 802.3ad Link Aggregation Control Protocol \;(LACP) for legacy BIOS expansion ROM (Flexboot).\;


name: client_identifier
tlv_name: nv_rom_ib_dhcp_conf
offset: 0x0.24
size: 0x0.4
type: ENUM
textual_values: ROM_DEFAULT=0x0,NO_CLIENT_IDENTIFIER=0x1,SEND_CLIENT_IDENTIFIER=0x2
description:
Select if the expansion ROM should add a Client Identi\;fier to DHCP DISCOVER and REQUEST packets over \;InfiniBand.\;0x0: ROM_DEFAULT \;0x1: NO_CLIENT_IDENTIFIER\;0x2: SEND_CLIENT_IDENTIFIER\;When set, the UEFI driver modifies the DHCP packet sent \;by the upper layers.


name: boot_to_target
tlv_name: nv_rom_iscsi_general_conf
offset: 0x0.22
size: 0x0.2
type: ENUM
textual_values: ENABLED=0x0,DISABLED=0x1,ONE_TIME_DISABLED=0x2
description:
Boot to iSCSI target after connection\;0x0: ENABLED - Boot from target\;0x1: DISABLED - Don"t boot from target (target will be \;hooked if configured and iscsi_keep_san_dev_en is set)\;0x2: ONE_TIME_DISABLED - Used for installing a new \;OS on the ISCSI target. Flexboot will not boot from the \;target once (e.g. DISABLED), and then will automatically \;change the value to ENABLED.


name: lun_busy_retry_count
tlv_name: nv_rom_iscsi_general_conf
offset: 0x8.0
size: 0x0.8
type: UNSIGNED
description:
Number of connection attempts to make if the iSCSI tar\;get is busy. Valid values are between 0 and 60.


name: iscsi_drive_num
tlv_name: nv_rom_iscsi_general_conf
offset: 0x8.16
size: 0x0.8
type: ENUM
textual_values: HDD1=0x80,HDD2=0x81,HDD3=0x82,HDD4=0x83
description:
The HDD number for the hooked iSCSI target in legacy \;BIOS int13 drive table.\;0x80: HDD1\;0x81: HDD2\;0x82: HDD3\;0x83: HDD4


name: value
tlv_name: nv_rom_iscsi_initiator_ip_addr
offset: 0x0.24
size: 0x10.0
type: STRING
description:
iSCSI initiator IPv4 address in dotted decimal notation \;(Flexboot) \;xuefi: IscsiInitiatorIpv4Addr


name: value
tlv_name: nv_rom_iscsi_initiator_subnet_mask
offset: 0x0.24
size: 0x10.0
type: STRING
description:
iSCSI initiator IPv4 subnet mask in dotted decimal notation \;(Flexboot)\;xuefi: IscsiInitiatorSubnet


name: value
tlv_name: nv_rom_iscsi_initiator_gateway
offset: 0x0.24
size: 0x10.0
type: STRING
description:
IPv4 gateway for the iSCSI initiator in dotted decimal nota\;tion (Flexboot)\;xuefi: IscsiInitiatorIpv4Gateway


name: value
tlv_name: nv_rom_iscsi_initiator_primary_dns_addr
offset: 0x0.24
size: 0x10.0
type: STRING
description:
Primary IPv4 DNS for iSCSI initiator in dotted decimal \;notation (Flexboot)\;xuefi: IscsiInitiatorIpv4PrimDns


name: value
tlv_name: nv_rom_iscsi_initiator_secondary_dns_addr
offset: 0x0.24
size: 0x10.0
type: STRING
description:
Secondary IPv4 DNS for iSCSI initiator in dotted decimal \;notation. (Flexboot)\;xuefi: IscsiInitiatorIpv4SecDns


name: value
tlv_name: nv_rom_iscsi_initiator_name
offset: 0x0.24
size: 0xe0.0
type: STRING
description:
This configuration sets the initiator name for iSCSI boot. \;According to the iSCSI RFC (3270) the name has to be \;UTF-8 encoded, with total length that does not exceed  223 \;bytes. It allows international characters, but prohibits the \;use of invisible characters, such as whitespace characters. \;(Flexboot)\;xuefi: IscsiInitiatorName


name: ipv4_dhcp_en
tlv_name: nv_rom_iscsi_dhcp
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When enabled, Flexboot attempts to discover IPv4 configu\;ration for iSCSI through DHCP.\;xuefi: TcpIpViaDhcp


name: value
tlv_name: nv_rom_iscsi_connect_to_first_target
offset: 0x0.24
size: 0x8.0
type: STRING
description:
When the string is "Enabled", Flexboot attempta to connect \;to the first ISCSI target. Other legal value is "Disabled"


name: value
tlv_name: nv_rom_iscsi_first_target_port
offset: 0x0.24
size: 0x8.0
type: STRING
description:
TCP port for the first iSCSI target (Flexboot)\;Decimal integer in ASCII format up to 5 digits (1-65536).


name: value
tlv_name: nv_rom_iscsi_connect_to_second_target
offset: 0x0.24
size: 0x8.0
type: STRING
description:
When the string is "Enabled", Flexboot attempts to connect \;to the first ISCSI target. Other legal value is "Disabled"


name: value
tlv_name: nv_rom_iscsi_second_target_port
offset: 0x0.24
size: 0x8.0
type: STRING
description:
TCP port for the second iSCSI target (Flexboot)\;Decimal integer in ASCII format up to 5 digits (1-65536).


name: psid
tlv_name: file_applicable_to
offset: 0x0.24
size: 0x10.0
type: STRING
description:
The PSID of the NIC that this file is applicable for. This \;ASCII string must be zero terminated if shorter than 16 \;characters.


name: psid_branch
tlv_name: file_applicable_to
offset: 0x10.24
size: 0x10.0
type: STRING
description:
The PSID-BRANCH that this file is applicable to. This \;ASCII string must be zero terminated if shorter than 16 \;characters. If PSID-Branch is not defined, the string is \;empty.


name: keypair_uuid
tlv_name: file_signature
offset: 0x10.24
size: 0x10.0
type: BYTES
description:
The UUID of the key-pair used for signing this file. An all \;zero UUID means that the signature is a SHA256 of the \;image.


name: auth_type
tlv_name: file_public_key
offset: 0x0.0
size: 0x0.8
type: ENUM
textual_values: INVALID_ENTRY=0x0,SHA256_DIGEST=0x1,_2048BIT_RSASSA_PKCS1_v1_5_WITH_SHA256=0x3
description:
The authentication mechanism used with this key\;0x0: INVALID_ENTRY\;0x1: SHA256_DIGEST\;0x3: _2048BIT_RSASSA_PKCS1_v1_5_WITH_SHA256


name: public_key_exp
tlv_name: file_public_key
offset: 0xC.0
size: 0x4.0
type: UNSIGNED
description:
The public key exponent.\;In most cases, the standard exponent (65537) will be used \;(per RFC4871).


name: auth_type
tlv_name: file_public_key_4096_a
offset: 0x0.0
size: 0x0.8
type: ENUM
description:
The authentication mechanism used with this key\;0x0: INVALID_ENTRY\;0x1: SHA256_DIGEST - not supported for this Key.\;0x3: _2048BIT_RSASSA_PKCS1_v1_5_WITH_SHA256 \;- not supported for this Key.\;0x4: _4096BIT_RSASSA_PKCS1_v1_5_WITH_SHA512

textual_values:
INVALID_ENTRY=0x0,SHA256_DIGEST=0x1,_2048BIT_RSASSA_PKCS1_v1_5_WITH_SHA256=0x3,_4096BIT_RSASSA_PKCS1_v1_5_WITH_SHA512=0x4


name: public_key_exp
tlv_name: file_public_key_4096_a
offset: 0xC.0
size: 0x4.0
type: UNSIGNED
description:
The public key exponent.\;In most cases, the standard exponent (65537) will be used \;(per RFC4871).\;


name: p2p_ordering_mode
tlv_name: nv_pci_conf
offset: 0x0.12
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,SECURE_NONE=0x1,SECURE_TRUST=0x2,SECURE_ALL=0x3
mlxconfig_name: P2P_ORDERING_MODE
dependency: $nv_pci_cap.p2p_ordering_mode_supported==1
description:
PCI Peer-to-Peer ordering security mode, between read requests \;completions and writes.\;0x0: DEVICE_DEFAULT\;0x1: SECURE_NONE - no protection/no peer-to-peer\;0x2: SECURE_TRUST - protect untrusted functions\;0x3: SECURE_ALL - protect all functions


name: dynamic_vf_msix
tlv_name: nv_pci_conf
offset: 0x0.23
size: 0x0.1
type: BOOL
mlxconfig_name: DYNAMIC_VF_MSIX_TABLE
dependency: $nv_pci_cap.dynamic_vf_msix_supported!=0
description:
When set to TRUE, the device will support allocation of MSI-Xs \;to VFs by the PF, after SR-IOV is enabled (while the VF is \;down).


name: ibm_tunneled_atomic_en
tlv_name: nv_pci_conf
offset: 0x0.27
size: 0x0.1
type: BOOL
mlxconfig_name: IBM_TUNNELED_ATOMIC_EN
dependency: ($nv_pci_cap.ibm_tunneled_atomic_supported!=0)
description:
Enable IBM's Tunneled Atomic feature. Supported only when \;NV_PCI_CAP.ibm_tunneled_atomic_supported is set.


name: force_eth_subclass
tlv_name: nv_pci_conf
offset: 0x0.29
size: 0x0.1
type: BOOL
mlxconfig_name: FORCE_ETH_PCI_SUBCLASS
description:
Force the PCI function identifier with Ethernet subclass (00h). \;Supported only when ADVANCED_PCI_SETTINGS is set.

dependency:
($nv_pci_cap.force_eth_subclass_supported!=0)&&($nv_pci_conf.advanced_pci_settings!=0)&&($nv_pci_cap.advanced_pci_settings_supported!=0)


name: ibm_capi_en
tlv_name: nv_pci_conf
offset: 0x0.30
size: 0x0.1
type: BOOL
mlxconfig_name: IBM_CAPI_EN
description:
Enable IBM's Coherent Accelerator Processor Interface (CAPI) \;mode. Supported only when ADVANCED_PCI_SETTINGS is \;set.

dependency:
($nv_pci_cap.ibm_capi_supported!=0)&&($nv_pci_conf.advanced_pci_settings!=0)&&($nv_pci_cap.advanced_pci_settings_supported!=0)


name: safe_mode_threshold
tlv_name: safe_mode_conf
offset: 0x0.0
size: 0x0.8
type: UNSIGNED
mlxconfig_name: SAFE_MODE_THRESHOLD
dependency: $safe_mode_conf.safe_mode_enable == 1
description:
Default value of the threshold for failed driver loads (driver load \;was not detected between reboots). When crossed, the device will \;load in Safe Mode with some default configurations, suspected as \;possible causes for driver load fail.


name: safe_mode_enable
tlv_name: safe_mode_conf
offset: 0x0.30
size: 0x0.1
type: BOOL
mlxconfig_name: SAFE_MODE_ENABLE
dependency: ignore_dependency
description:
Enable Safe Mode activation after crossing a threshold of consec\;utive failed boots (no driver load).


